library ieee;
use ieee.std_logic_1164.all;

entity signext is
port ( a : in std_logic_vector(15 downto 0);
        y : out std_logic_vector(31 downto 0));
end entity;

architecture arch of signext is
begin
    process (a)
    begin
        for i in 15 downto 0 loop
           y(i) <= a(i);
        end loop;
        
        if (a(15) = '1') then
        	for i in 31 downto 16 loop
           		y(i) <= '1';
        	end loop;
        else
        	for i in 31 downto 16 loop
           		y(i) <= '0';
        	end loop;
        end if;
    end process;
end architecture;
